Advisory CTO: Mitsumasa Koyanagi, Ph.D., Prof.
IEEE MEDAL LAUREATE / IEEE FELLOW

Professor. Koyanagi in Tohoku University is a well-known IEEE fellow as a pioneer of 3D Stacking LSI technology. He has been researching and developing 3D Stacking process at Hitachi, Ltd, Xerox Palo Alto Research Center, Hiroshima University and Tohoku University over 35 years. He is called "MR.DRAM" from his enormous invention of Stacked capacitor DRAM technology.  

1974: Doctor of Electronic Engineering,
           Tohoku University, Japan
1974: Hitachi, Ltd., Research Center
           Researched DRAM process/device technology.
           Invented Stacked Capacitor DRAM
1985: Xerox Palo Alto Research Center
           Researched sub-micron device, TFT,
           and digital/analog design
1988: Professor of Integrated System Research Center,
           Hiroshima University
1994: Professor of Intelligent Machine Engineering,
           Tohoku University
1995: Professor of Intelligent Machine Engineering,
           Graduate School of Tohoku University Chairman
           of Venture Lab, Tohoku University
2010: Professor of New Industry Creation Hatchery Center,
           Tohoku University  

(Prize-winning)
SSDM Award (1992)
IEEE Cledo Bruneti Award (1996)
Minister of Sciense and Technology Agency Award (2002), etc

(Publication)
Physics of VLSI Device (Maruzen)
Sub-micron Technology I, II (Maruzen), etc