Micro-Bump

T-Micro 3D-Stacking LSI process technology

Micro-Bump:

Fig-1 shows our stacked-TEG chip stacking an upper chip and a lower chip, which are joined with an adhesive and 5 μm-pitch μ-bumps, to integrate 10^4 daisy chain pattern.

Fig-1：Stacked TEG chip by μ-bumps

The bump size is 2 μm×2 μm. The adhesive is injected after temporary bonding is achieved. The 0.5 μm gap between two chips is completely filled with the adhesive. The bump resistance is less than 0.2 Ω. The results of the temperature cycle test (-65 ℃/150 ℃) revealed that there was no degradation up to 500 cycles. Since the bumps completely melted, the bump resistance did no increase even at a slight misalignment.

Fig-2 is a SEM cross-sectional image of a prototype chip manufactured in T-Micro’s 3D-Stacking LSI prototype manufacturing service by use of our μ-bumps. The bump size is 3 μm×3 μm with 13 μm-pitch.

Fig-2：SEM cross-sectional image of a prototype chip

More info: info@t-microtec.com

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T-Micro is the unique and advanced 3D/2.5D IC process and MEMS process-oriented company, originated in Tohoku University.
As an exclusive technical representative of GINTI "Global Integration Initiative" facility, we provide worldwide customers with 3D/ 2.5D/ MEMS full foundry service as well as partial process service by use of a complete line of state-of-the-art 200 and 300mm equipment in a cost-effective and short-TAT way for R/D, prototype, and small volume production.

東北マイクロテック(T-Micro)は、最先端の積層型三次元IC(3D-IC)技術をベースにした会社で、微細TSV(貫通配線)、マイクロバンプ接合等の新技術を入れ、今後のIT需要の拡大に呼応して、従来のICチップに高性能・高機能・小型化・省電力化といった新しい機能を付加します。新規の積層型センサの開発と並行してお客様に以下のサービスを提供致します。